Freescale Semiconductor /MKL28T7_CORE1 /ASMC /SRS

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as SRS

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0)WAKEUP 0 (0)WDOG1 0 (0)RES 0 (0)POR 0 (0)LOCKUP 0 (0)SW 0 (0)SACKERR

SW=0, SACKERR=0, LOCKUP=0, POR=0, RES=0, WDOG1=0, WAKEUP=0

Description

System Reset Status Register

Fields

WAKEUP

Low Leakage Wakeup Reset

0 (0): Reset not caused by LLWU module wakeup source

1 (1): Reset caused by LLWU module wakeup source

WDOG1

Watchdog

0 (0): Reset not caused by watchdog timeout

1 (1): Reset caused by watchdog timeout

RES

Chip Reset not POR

0 (0): Chip Reset did not occur

1 (1): Chip Reset caused by a source other than POR occured

POR

Power-On Reset

0 (0): Reset not caused by POR

1 (1): Reset caused by POR

LOCKUP

Core 1 Lockup

0 (0): Reset not caused by core LOCKUP event

1 (1): Reset caused by core LOCKUP event

SW

Software

0 (0): Reset not caused by software setting of SYSRESETREQ bit

1 (1): Reset caused by software setting of SYSRESETREQ bit

SACKERR

Stop Mode Acknowledge Error Reset

0 (0): Reset not caused by peripheral failure to acknowledge attempt to enter stop mode

1 (1): Reset caused by peripheral failure to acknowledge attempt to enter stop mode

Links

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